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| HIP2106 Data Sheet August 1999 File Number 4406.2 100V/1A Peak, Low Cost, High Frequency Half Bridge Driver The HIP2106 is a high frequency, 100V Half Bridge N-Channel MOSFET driver IC, available in 8 lead plastic SOIC. The low-side and high-side gate drivers are independently controlled and matched to 8ns. This gives the user maximum flexibility in dead-time selection and driver protocol. Undervoltage protection on both the low-side and high-side supplies force the outputs low. An on-chip diode eliminates the discrete diode required with other driver ICs. A new levelshifter topology yields the low-power benefits of pulsed operation with the safety of DC operation. Unlike some competitors, the high-side output returns to its correct state after a momentary undervoltage of the high-side supply. Features * Drives N-Channel MOSFET Half Bridge * Space Saving SO8 Package * Bootstrap Supply Max Voltage to 116VDC * On-Chip 1 Bootstrap Diode * Fast Propagation Times Needed for Multi-MHz Circuits * Drives 1000pF Load at 500kHz with Rise and Fall Times of Typically 20ns * CMOS Input Thresholds for Improved Noise Immunity * Independent Inputs for Non-Half Bridge Topologies * No Start-Up Problems * Outputs Unaffected by Supply Glitches, HS Ringing Below Ground, or HS Slewing at High dv/dt Ordering Information PART NUMBER HIP2106IB HIP2106IP TEMP. RANGE (oC) -40 to 85 -40 to 85 PACKAGE 8 Ld SOIC 8 Ld PDIP PKG. NO. M8.15 E8.3 * Low Power Consumption * Wide Supply Range * Supply Undervoltage Protection * 3 Output Resistance Pinout HIP2106 (SOIC, PDIP) TOP VIEW VDD HB HO HS 1 2 3 4 8 7 6 5 LO VSS LI HI Applications * Telecom Half Bridge Power Supplies * Avionic DC-DC Converters * Two-Switch Forward Converters * Active Clamp Forward Converters Application Block Diagram +12V +100V VDD HB SECONDARY CIRCUIT HI CONTROL DRIVE HI HO HS DRIVE LO LO PWM CONTROLLER LI HIP2106 VSS REFERENCE AND ISOLATION 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 HIP2106 Functional Block Diagram 2 HB VDD 1 UNDER VOLTAGE LEVEL SHIFT DRIVER 4 HI 5 HS 3 HO UNDER VOLTAGE DRIVER LI VSS 6 7 8 LO Other Applications +48V +12V PWM HIP 2106 SECONDARY CIRCUIT ISOLATION FIGURE 1. TWO-SWITCH FORWARD CONVERTER +48V +12V SECONDARY CIRCUIT PWM HIP 2106 ISOLATION FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE CLAMP 2 HIP2106 Absolute Maximum Ratings Supply Voltage, VDD, VHB-VHS . . . . . . . . . . . . . . . . . . . -0.3V to 18V LI and HI Voltages . . . . . . . . . . . . . . . . . . . . . . . . .-3V to VDD +0.3V Voltage on LO . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Voltage on HO . . . . . . . . . . . . . . . . . . . . . . VHS -0.3V to VHB +0.3V Voltage on HS (Continuous) . . . . . . . . . . . . . . . . . . . . . -1V to 110V Voltage on HB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +118V Average Current in VDD to HB Diode. . . . . . . . . . . . . . . . . . . 100mA ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 (1kV) Thermal Information Thermal Resistance (Typical, Note 1) JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 HS Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V/ns Maximum Power Dissipation at 25oC in Free Air . . . . . . . . . .780mW Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Junction Temperature Range . . . . . . . . . -55oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (Lead Tips Only) Recommended Operating Conditions Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . +9V to +16.5V Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V Voltage on HS . . . . . . . . . . . . . . . (Repetitive Transient) -5V to 105V Voltage on HB. . . VHS +8V to VHS +16.5V and VDD -1V to VDD +100V CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. JA is measured with the component mounted on an evaluation PC board in free air. 2. All Voltages Relative to Pin 4, VSS Unless Otherwise Specified. Electrical Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified TJ = 25oC PARAMETER SUPPLY CURRENTS VDD Quiescent Current VDD Operating Current Total HB Quiescent Current Total HB Operating Current HB to VSS Current, Quiescent HB to VSS Current, Operating INPUT PINS Low Level Input Voltage Threshold High Level Input Voltage Threshold Input Voltage Hysteresis Input Pulldown Resistance UNDER VOLTAGE PROTECTION VDD Rising Threshold VDD Threshold Hysteresis HB Rising Threshold HB Threshold Hysteresis BOOT STRAP DIODE Low-Current Forward Voltage High-Current Forward Voltage Dynamic Resistance LO GATE DRIVER Low Level Output Voltage High Level Output Voltage Peak Pullup Current Peak Pulldown Current HO GATE DRIVER Low Level Output Voltage High Level Output Voltage Peak Pullup Current VOLH VOHH IOHH IHO = 100mA IHO = -100mA, VOHH = VHB-VHO VHO = 0V 0.25 0.25 1 0.3 0.3 0.4 0.4 V V A VOLL VOHL IOHL IOLL ILO = 100mA ILO = -100mA, VOHL = VDD-VLO VLO = 0V VLO = 12V 0.25 0.25 1 1 0.3 0.3 0.4 0.4 V V A A VDL VDH RD IVDD-HB = 100A IVDD-HB = 100mA IVDD-HB = 100mA 0.45 0.7 0.8 0.55 0.8 1 0.7 1 1.5 V V VDDR VDDH VHBR VHBH 7 6.5 7.3 0.5 6.9 0.4 8 7.5 6.5 6 8.5 8 V V V V VIL VIH VIHYS RI 4 5.4 5.8 0.4 200 8 3 100 9 500 V V V k IDD IDDO IHB IHBO IHBS IHBSO LI = HI = 0V f = 500kHz LI = HI = 0V f = 500kHz VHS = VHB = 116.5V f = 500kHz 0.1 1.5 0.1 1.5 0.05 0.7 0.15 2.5 0.15 2.5 1 0.2 3 0.2 3 10 mA mA mA mA A mA SYMBOL TEST CONDITIONS MIN TYP MAX TJ = -40oC TO 125oC MIN MAX UNITS 3 HIP2106 Electrical Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified (Continued) TJ = 25oC PARAMETER Peak Pulldown Current SYMBOL IOLH TEST CONDITIONS VHO = 12V MIN TYP 1 MAX TJ = -40oC TO 125oC MIN MAX UNITS A Switching Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified TJ = 25oC MIN CL = 1000pF CL = 0.1F CL = IRFR120 CL = IRFR120 TYP 40 40 40 40 4 4 20 1.0 40 20 20 MAX 70 70 70 70 16 16 1.2 TJ = - 40oC TO 125oC MIN MAX 90 90 90 90 20 20 1.6 100 UNITS ns ns ns ns ns ns ns us ns ns ns ns PARAMETER Lower Turn-Off Propagation Delay (LI Falling to LO Falling) Upper Turn-Off Propagation Delay (HI Falling to HO Falling) Lower Turn-On Propagation Delay (LI Rising to LO Rising) Upper Turn-On Propagation Delay (HI Rising to HO Rising) Delay Matching: Lower Turn-On and Upper Turn-Off Delay Matching: Lower Turn-Off and Upper Turn-On Either Output Rise/Fall Time Either Output Rise/Fall Time (3V to 9V) Either Output Rise Time Driving DMOS Either Output Fall Time Driving DMOS Minimum Input Pulse Width that Changes the Output Bootstrap Diode Turn-On or Turn-Off Time SYMBOL tLPHL tHPHL tLPLH tHPLH tMON tMOFF tRC , tFC tR , tF tRD tFD tPW tBS TEST CONDITIONS Pin Descriptions PIN NUMBER 1 2 3 4 5 6 7 8 SYMBOL VDD HB HO HS HI LI VSS LO DESCRIPTION Positive Supply to lower gate drivers. De-couple this pin to VSS (Pin 7). Bootstrap diode connected to HB (pin 2). High-Side Bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin. Bootstrap diode is on-chip. High-Side Output. Connect to gate of High-Side power MOSFET. High-Side Source connection. Connect to source of High-Side power MOSFET. Connect negative side of bootstrap capacitor to this pin. High-Side input. Low-Side input. Chip negative supply, generally will be ground. Low-Side Output. Connect to gate of Low-Side power MOSFET. Timing Diagrams LI HI, LI tHPLH , tLPLH HO, LO tHPHL, tLPHL HI LO tMON HO tMOFF FIGURE 3. FIGURE 4. 4 HIP2106 Typical Performance Curves 10 10 IDDO , IHBO (mA) IHBSO (mA) 1 1 T = 150oC 0.1 T = -40oC 0.1 T = 150oC T = 125oC T = 25oC T = -40oC 0.01 10 0.01 50 100 FREQUENCY (kHz) 500 10 T = 125oC T = 25oC 100 FREQUENCY (kHz) 1000 FIGURE 5. OPERATING CURRENT vs FREQUENCY FIGURE 6. LEVEL SHIFTER CURRENT vs FREQUENCY 500 500 VHB = VDD = 9V 400 VOHL, VOHH (mV) VHB = VDD = 12V VHB = VDD = 16.5V 300 VOLL , VOLH (mV) VHB = VDD = 14V 400 VHB = VDD = 9V VHB = VDD = 12V VHB = VDD = 14V VHB = VDD = 16.5V 300 200 200 100 -50 0 50 TEMPERATURE (oC) 100 150 100 -50 0 50 TEMPERATURE (oC) 100 150 FIGURE 7. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE FIGURE 8. LOW LEVEL OUTPUT VOLTAGE vs TEMPERATURE 7.6 0.54 0.5 VHBH , VDDH (mV) VDDR 0.46 0.42 0.38 VHBH 0.34 0.3 -50 VDDH 7.4 VHBR , VDDR (mV) 7.2 7.0 VHBR 6.8 6.6 -50 0 50 TEMPERATURE (oC) 100 150 0 50 TEMPERATURE (oC) 100 150 FIGURE 9. UNDERVOLTAGE LOCKOUT THRESHOLD vs TEMPERATURE FIGURE 10. UNDERVOLTAGE LOCKOUT HYSTERESIS vs TEMPERATURE 5 HIP2106 Typical Performance Curves 60 tLPLH , tLPHL, tHPLH , tHPHL (ns) tHPHL tHPLH 50 tLPHL IHO , ILO (A) tLPLH 1.5 (Continued) 2.5 2.0 1.0 40 0.5 30 -50 0 0 50 TEMPERATURE (oC) 100 150 0 2 4 6 VHO , VLO (V) 8 10 12 FIGURE 11. PROPAGATION DELAYS vs TEMPERATURE FIGURE 12. PULLUP CURRENT vs OUTPUT VOLTAGE 2.5 1 0.1 FORWARD CURRENT (A) 0 2 4 6 VLO , VHO (V) 8 10 12 0.01 0.001 1*10-4 1*10-5 1*10-6 0.3 2.0 ILO , IHO (A) 1.5 1.0 0.5 0 0.4 0.5 0.6 FORWARD VOLTAGE (V) 0.7 0.8 FIGURE 13. PULLDOWN CURRENT vs OUTPUT VOLTAGE FIGURE 14. BOOTSTRAP DIODE I-V CHARACTERISTICS 60 50 IHB vs VHB IDD , IHB (A) 40 IDD vs VDD 30 20 10 0 0 5 10 VDD, VHB (V) 15 FIGURE 15. BIAS CURRENT vs VOLTAGE 6 HIP2106 Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 E8.3 (JEDEC MS-001-BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL -B- MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 9.01 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 10.16 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93 MIN 0.015 0.115 0.014 0.045 0.008 0.355 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280 -AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E A A1 A2 B B1 C D D1 E -C- eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). E1 e eA eB L N 0.100 BSC 0.300 BSC 0.115 8 0.430 0.150 - 2.54 BSC 7.62 BSC 10.92 3.81 8 2.93 7 HIP2106 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 L A1 B C D E A1 0.10(0.004) C e H h L N 0.050 BSC 0.2284 0.0099 0.016 8 0o 8o 0.2440 0.0196 0.050 1.27 BSC 5.80 0.25 0.40 8 0o 6.20 0.50 1.27 e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 8 |
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